Integrated circuits (ICs) can be damaged by electrostatic discharge (ESD) events, in which large currents flow through the device. These ESD events often involve situations where an IC becomes charged and discharges to ground. Additionally, ESD events typically involve discharge of current between one or more pins or pads exposed to the outside of an IC chip. During an ESD event, current may flow through vulnerable circuitry in the IC that may not be designed to carry such currents. The vulnerability of IC chips to ESD events has created an important need for ESD protection circuits. As a result of the need to protect IC chips from ESD events, ESD protection circuits are often added to the integral design of IC chips to protect functional circuits (e.g., input devices, output devices) from ESD events.
ESD events are only one type of stress that may be experienced by a functional circuit. Other types of stress can include other forms of electrical overstress (EOS), overvoltage stress, overcurrent stress and latchup. Protection circuits for these types of stress are often added to the integral design of IC chips. The protection circuits are evaluated during testing to determine whether the protection circuitry protects the protected circuitry within a certain predetermined limit. However, present stress protection circuit development does not incorporate any mechanism or methodology to assess the efficacy of the protection circuit to prevent the protected circuit from subtle parametric degradation.